The Design Warrior's Guide to FPGAs: Devices, Tools and FlowsElsevier, 16 juin 2004 - 542 pages Field Programmable Gate Arrays (FPGAs) are devices that provide a fast, low-cost way for embedded system designers to customize products and deliver new versions with upgraded features, because they can handle very complicated functions, and be reconfigured an infinite number of times. In addition to introducing the various architectural features available in the latest generation of FPGAs, The Design Warrior’s Guide to FPGAs also covers different design tools and flows. This book covers information ranging from schematic-driven entry, through traditional HDL/RTL-based simulation and logic synthesis, all the way up to the current state-of-the-art in pure C/C++ design capture and synthesis technology. Also discussed are specialist areas such as mixed hardward/software and DSP-based design flows, along with innovative new devices such as field programmable node arrays (FPNAs). Clive "Max" Maxfield is a bestselling author and engineer with a large following in the electronic design automation (EDA)and embedded systems industry. In this comprehensive book, he covers all the issues of interest to designers working with, or contemplating a move to, FPGAs in their product designs. While other books cover fragments of FPGA technology or applications this is the first to focus exclusively and comprehensively on FPGA use for embedded systems.
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Table des matières
| 1 | |
| 9 | |
| 25 | |
4 Alternative FPGA Architectures | 57 |
5 Programming SConfiguringw an FPGA | 99 |
6 Who Are All the Players? | 115 |
7 FPGA Versus ASIC Design Styles | 121 |
8 SchematicBased Design Flows | 133 |
18 Migrating ASIC Designs to FPGAs and Vice Versa | 293 |
19 SimulationI SynthesisI VerificationI etcB Design Tools | 299 |
20 Choosing the Right Device | 343 |
21 Gigabit Transceivers | 353 |
22 Reconfigurable Computing | 373 |
23 FieldProgrammable Node Arrays | 381 |
24 Independent Design Tools | 397 |
25 Creating an OpenSourceBased Design Flow | 407 |
9 HDLBased Design Flows | 153 |
10 Silicon Virtual Prototyping for FPGAs | 179 |
11 CCbb etcBased Design Flows | 193 |
12 DSPIBased Design Flows | 217 |
13 Embedded ProcessorBased Design Flows | 239 |
14 Modular and Incremental Design | 259 |
15 HighSpeed Design and Other PCB Considerations | 267 |
16 Observing Internal Nodes in an FPGA | 277 |
17 Intellectual Property | 287 |
26 Future FPGA Developments | 419 |
back matter | 429 |
DeepSubmicron Delay Effects 101 | 443 |
Linear Feedback Shift Registers 101 | 465 |
Glossary | 485 |
About the Author | 525 |
| 527 | |
Autres éditions - Tout afficher
The Design Warrior's Guide to FPGAs: Devices, Tools and Flows Clive Maxfield Aucun aperçu disponible - 2004 |
The Design Warrior's Guide to FPGAs: Devices, Tools and Flows Clive Maxfield Aucun aperçu disponible - 2004 |
Expressions et termes fréquents
algorithms antifuse applications architectures ASIC design associated bits C/C++ capacitance chapter chip circuit board clock signal complex components configuration cells configuration data contain CPLDs create design engineers design flow discussed electronic embedded environment EPROM equivalent example flip-flop formal verification FPGA design FPGA vendors gate-level netlist hardware implementation input integrated circuit interconnect interface JTAG language level of abstraction LFSR load logic function logic gates logic simulator logic synthesis logic values microprocessor microprocessor core multiple multiplexer netlist nodes output perform pins place-and-route PLDs Pn-Pn delays problem processor programmable logic blocks pronounced by spelling reconfigured refers representation result schematic signal silicon simple Simulink source code specific SRAM SRAM-based standard switching threshold synthesis engine synthesis tools SystemC SystemVerilog technique term testbench things tion today’s tracks transceiver transistors typically Verilog VHDL wires Xilinx
Fréquemment cités
Page 30 - RAM 5 address 0 address 1 address 2 address 3 address 4 address 5 address 6 address 7 address 8 address 9 address 10 Figure 10.