Computer Hardware Description Languages and Their Applications: Proceedings of the IFIP WG 10.2 Seventh International Conference on Computer Hardware Description Languages and Their Applications, Tokyo, Japan, 29-31 August 1985, Volume 5Cees-Jan Koomen, Tōru Motooka North-Holland, 1985 - 493 pages Hardbound. The papers of this seventh conference reflect the gradual shift from the original emphasis on the uses of language design to describe hardware, toward more formal techniques for specification and verification.This volume highlights the following topics: - Languages to specify and describe hardware design, to reason about timing and functional behaviour, and to support modelling and performance evaluation - Synthesis and verification of systems as means of support for the design process, and as a guarantee of design consistency and functional correctness - Tool Integration aspects such as the representation of design information, and the putting together of tools within a coherent design environment. |
Table des matières
SPECIFICATION | 1 |
VERIFICATION | 2 |
VERIFICATION | 11 |
Droits d'auteur | |
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Expressions et termes fréquents
abstract specification adder algorithm Applications approach architecture automatically axioms behavior block bool boolean CAD system CASCADE CHDL circuit clock compiler complex components condition connected construction data path data types defined definition delay described Design Automation design method design process diagram digital systems DSTL evaluation example execution expression fault fifo Figure formal formal verification function gate graph Hardware Description Languages hierarchical IEEE implementation input instance instruction set integrated interconnection interface logic design logic simulation logic synthesis loop machine description memory microprogram module node object operations output package parameters PARLOG performance Petri Nets ports primitive problem Proc procedure processor programming language Prolog realization specification register transfer register transfer level reset semantics sequence signal structure submodules synchronous techniques temporal logic test pattern testable transition truth table variables verification View Type VLSI VLSI design wire